A Study of Cache Performance in Java Virtual Machines

APPROVED BY SUPERVISING COMMITTEE _________________________ _________________________ iii Acknowledgements I would like to thank Dr. Lizy John for her valuable guidance and advice during the course of this work. I would also like to express my gratitude to Dr Doug Burger for agreeing to be the reader for my report. I also want to thank all the members of the Laboratory for Computer Architecture for all their invaluable help and Java is a widely used programming language due to the portability and machine independent nature of bytecodes. Considering the fact that we have quite a few options available in the execution of Java bytecodes, it is very important to have a clear understanding of the runtime performance aspects in each of the modes. This work attempts to characterize the cache performance of the interpreted, JIT and mixed modes. This study delves deep into the reasons for poor data cache performance in JITs by separating the virtual machine into functionally disparate components and studying cache performance in each of the components. The JIT mode of execution of bytecodes results in a large reduction in the number of native instructions executed but the price to be paid is in the form of poor cache performance. The instruction cache performance in the JIT compilation is always worse than that in the interpreted mode. Data writes exhibit extremely poor performance in JIT modes of execution and the miss rates are on an average 38%. Intelligent translation of Java methods implemented by dynamic profiling in mixed-mode execution engines like HotSpot does not change the overall cache performance of the JVM. We hope that this study serves as a pointer to optimizing specific v sections of the code in the JVM. Our results indicate that the code translation routines of the JIT are good candidates for optimization. We also hope that it would be a guide for architectural enhancements that can mitigate the effect of poor cache performance. An example of such an enhancement could be in the form of directly generating code into an instruction cache that accommodates write operations.